FFT IP Core Generator

FFT IP Core banner image

This project’s goal is to make integrating a fast Fourier transform (FFT) processing core into your project incredibly simple. If you are reading this, then you are most likely well aware of the many uses for an FFT in an FPGA.

Background

I was going to use an FFT core for my senior project, but I had a difficult time integrating a proprietary FFT core. The User Guide for the core did not give me enough detail for me to build a proper interface. Even if I could have gotten it working, I didn’t (and still don’t) have the money to purchase a license for the core, so it would be severly limited in its functionality.

My senior project research taught me a lot about FFT processing in a hardware platform, which got me thinking about how I could build my own core. However, I didn’t want to just make a single core for my own specific application, I wanted the functionality of generating an FFT processor of any length and bit-width. And that is how this FFT generator was born.

Features

  • Automatically calculates twiddle factors
  • Uses a high-performance implimentation of a Baugh-Wooley multiplier
    • Relatively new HPM reduction tree architecture 1
    • Good compromise between power usage and speed
    • Faster than conventional Baugh-Wooley multiplier 2
    • Faster than HPM Modified Booth multiplier 2
  • Length and width can be (nearly) any number
  • Generates clean, clear SystemVerilog code

Architecture

With the guidance of George Slade’s paper, along with some other internet resources, I have been working on an object-oriented, C++ library to configure and generate SystemVerilog compatible modules for use in any vendor’s FPGA.

The FFT core uses a custom-built multiplier. Specifically, a SystemVerilog implementation of the HPM-based Baugh-Wooley multiplier, as researched by H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Sjalander, D. Johansson, and M. Scholin. Refer to their paper Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity for more information. I have contacted Mr. Sjalander and received permission to impliment their multiplier design.

Status

Component Name C++ Code Written C++ Code Tested SV Synthesizes SV ModelSim Simulation Test
ROM picture picture picture picture
Twiddle ROM picture picture picture picture
Multiplier picture picture picture picture
RAM picture picture picture picture
2-port RAM picture picture picture picture
Butterfly Unit (BFU) picture picture picture picture
Top-level module picture picture picture picture
(op) Kogge-Stone Adder picture picture picture picture

More Information

At the moment, I am developing this project on Bitbucket. Right now, the repository is hidden/private, but when I make it public, you will be able to access it at the following URL.



  1. H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Själander, D. Johansson, M. Schölin. “Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity”. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS). Island of Kos, Greece, pp. 4-8, 21-24 May 2006. ^
  2. Jipsa Antony, Jyotirmoy Pathak. “DESIGN AND IMPLEMENTATION OF HIGH SPEED BAUGH WOOLEY AND MODIFIED BOOTH MULTIPLIER USING CADENCE RTL”. International Journal of Research in Engineering and Technology 03.08 (2014): 56-63. Web. 30 Jan. 2017. ^